Researchers at National Taiwan University have developed a unified model that explains how thickness, defects, interface quality, and roughness together control the behavior of ultrathin oxide transistors. The work, published in Small Structures, provides practical design rules for building low-leakage, normally-off devices suitable for future 3D chip stacking.
Better models are needed for better ultrathin transistors
As the semiconductor industry pushes toward three-dimensional chip stacking, engineers need transistors that can be built on top of existing circuits without damaging the layers below. That means the devices must be manufactured at relatively low temperatures, stay extremely thin, consume very little power, and still switch reliably.
Oxide semiconductors are attractive candidates for this role, but when they are thinned to only a few nanometers, their behavior becomes difficult to predict. Small changes in defects, interface quality, or surface roughness can strongly affect leakage current, threshold voltage, mobility, and long-term stability.
That uncertainty is the main problem addressed in the new study from National Taiwan University. Rather than focusing only on reporting device performance, the researchers built a unified analytical framework that explains how ultrathin indium-oxide-based transistors operate across the full switching range. The model connects several effects that are usually studied separately: ordinary band transport, current through electronic trap states, defect-assisted current at the dielectric interface, and mobility loss caused by surface roughness as the channel becomes atomically thin.
One framework for thickness, traps, interfaces, and roughness
To test the framework, the team studied transistors made from indium oxide and tungsten-doped indium oxide, also called IWO, with channel thicknesses ranging from about 2 to 13 nanometers. Their measurements showed that pure indium oxide becomes much harder to control in the ultrathin limit, while IWO performs more favorably.
But the central advance is not simply that one material works better than another. The key result is that the model can accurately reproduce the measured current-voltage characteristics and identify why the two materials behave differently.
Using this approach, the researchers extracted two especially important quantities: how many trap states are present and how broad their energy distribution is. These trap-related parameters turned out to be closely linked to the real device metrics engineers care about, including off-state leakage, switching sharpness, threshold shift, and mobility. The model also includes a thickness- and gate-dependent mobility term, allowing it to describe how roughness scattering becomes more severe when electrons are pushed closer to the gate dielectric in ultrathin channels.
A design tool, not just a fit to data
The study shows that tungsten doping improves the material in two ways. First, it suppresses unwanted carriers and lowers leakage current, making it easier to achieve normally off operation. Second, it reduces disorder and improves the interface with the gate dielectric, which helps preserve mobility and subthreshold behavior even when the channel is only 2 to 3 nanometers thick. Quantum-mechanical calculations supported the same picture by indicating a smoother and more coherent IWO interface.
The framework also helps explain reliability under electrical stress. In thicker devices, stress mainly changes the energy width of the trap distribution, which can even improve switching behavior. In ultrathin devices, the interface plays a bigger role, so stress more easily activates traps and shifts the operating voltage. By describing both regimes with the same physical picture, the model gives researchers a clearer way to interpret bias-stability measurements instead of treating them as isolated empirical results.
The broader value of the work is that it turns experimental measurements into a predictive design method. Instead of relying on trial and error, engineers can use the framework to understand how channel thickness, doping, disorder, and interface quality should be balanced to reach target device performance. That is especially important for back-end-of-line electronics, where transistors must be made at temperatures below 400°C and still meet strict requirements for leakage, switching, and stability.
Practical guidance for future 3D electronics
In simple terms, the paper shows that ultrathin oxide transistors cannot be designed by looking at thickness, material choice, or defect density one at a time. These factors are coupled, and a useful model has to treat them that way. The proposed unified framework does exactly that, offering a physically grounded way to describe present devices and guide the design of better ones for stacked-chip technologies.
"The main contribution of this work is a unified model that can accurately describe how ultrathin oxide transistors behave and show designers which material and thickness choices are most promising," says co-corresponding author Min-Hung Lee, Ph.D., professor of semiconductor devices, materials and hetero-integration at Graduate School of Advanced Technology, National Taiwan University.
"Our goal is to move from isolated device demonstrations toward a predictive framework for designing reliable, low-temperature transistors for future 3D integrated electronics."
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